To permit high density packaging of integrated circuits it is known to utilize a silicon substrate with bonding pads for connection to signal or power lines of the ICs and a network of conductors for making desired connections between the bonding pads. Custom circuit boards specifically designed for a given application can effectively meet the needs for such IC interconnection but are limited by economic considerations to large scale applications. The U.S. Pat. No. 4,866,508 to Eichelberger et al is an example of such a custom board. Standard horizontal conductor lines formed on the substrate comprise short line segments which are connectible together by links or to vertical lines through vias. The links and vertical lines are formed on a custom metallization layer. In the case where a relatively small production volume is planned, a preferred approach is to use a circuit board which is programmable after manufacture for a configuration which meets the circuit needs of the ICs.
Designing a programmable circuit board for general purpose use provides the challenge of placing bonding pads at locations which can be conveniently utilized by the IC connections and yet does not waste space. Because the die size of the ICs is not known in advance, the bonding pad layout must then be configured to allow wide flexibility of pad choice. Once a pad choice has been made for a given IC application, it is important that the pads be free from defects so that the choice is not compromised. While it is possible to substitute a neighboring good pad for a defective pad and adjust the circuit accordingly, that practice is not desirable since a constant pad configuration for a given product is preferred for testing the circuit after programming. That is, some test procedures for circuit boards rely on certifying that bonding pads at given locations are connected in the circuit to yield certain prescribed characteristics. It is thus desired to build a circuit board where every pad has a high probability of being good.
Examples of programmable interconnect architecture are already known. For example the U.S. Pat. No. 4,758,745 discloses a matrix of logic modules formed in a silicon substrate and interconnected by rows of horizontal and vertical connections lines. Each such line is made up of short line segments connected end-to-end by transistors and by programmable elements which comprise normally insulating material at each line junction which becomes conductive when a certain voltage is applied across the respective lines. Connections are programmable at line crossings due to a programmable element at each intersection. To apply programming voltage across the lines all the transistors in the respective lines must be conductive. An array of control lines is provided for transistor control. The requirement of the many transistors and their control lines limits the density of the connection lines and increases the probability of defective parts. Since the logic modules are built in, there is no concern for the efficient mating of bonding pads with IC dice placed on the substrate.
The U.S. Pat. No. 4,458,297 to Stopper et al entitled "Universal Interconnection Substrate", which is incorporated herein by reference, discloses a wafer-based substrate for connecting IC chips including two layers of patterned metal defining crossing lines selectively interconnected at line crossings by antifuses. The antifuses comprise vias through intervening insulator layers which contain amorphous silicon deposited as an insulator but programmable to a conductive state by the application of a threshold voltage across the antifuse. The signal interconnection network includes many bonding pads dispersed across the substrate and each pad connected to one pad line which extends either horizontally or vertically, and nets, each of which comprise an interconnected pair of horizontal and vertical lines connected to one pad at the edge of the substrate. Each pad line crosses each net and can be programmed to connect to any line.
Drawbacks to the Stopper et al configuration include high line capacitance, large die placement granularity, and scarcity of pads for high pinout dice. The high line capacitance is the direct consequence of long lines which may extend across the substrate and the number of such lines that are connected together. Granularity refers to the distance between pad groups within the substrate. If a die is slightly too big to fit within an array of pad groups, it must be assigned to the next larger array. A smaller distance between pad groups would waste less space. Another concern is that a given pad resource, i.e. a bonding pad and its associated line, is relatively large and thus subject to a greater probability of defects than would a small resource. The same is true of a net since it comprises two long lines connected together.
Later improvements to the Stopper et al approach reduced some of the problems. They used smaller substrates to limit line length and thereby reduce capacitance. As shown in FIG. 1, net lines 10 connected to external pads 12 ran only vertically except for some horizontal connecting links to side pads. Pad lines ran horizontally. Several pads 14 were connected to each pad line. One type of pad line 16 ran across the substrate from side to side and another type 18 crossed from one inside edge of a pad group to the other inside edge. The shorter lines resulted in lower capacitance. All line intersections are provided with antifuses; only the programmed antifuses 20 are shown in the drawing. Granularity was improved, giving improvement in die packing density. On the other hand, the assignment of several pads on each pad line restricts design flexibility, substrate size is limited to keep capacitance low, defect avoidance often requires changes to the wire bonding, and test time is long. Testing requires multiple setups of different probe cards; tooling is unique, or nearly so, for each member of the family.